TY - GEN
T1 - Dynamic pipeline-partitioned video decoding on symmetric stream multiprocessors
AU - Wu, Ming Ju
AU - Chen, Yan Ting
AU - Tsai, Chun-Jen
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/8
Y1 - 2015/9/8
N2 - In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture allows the processor cores to cooperate efficiently in a fine-grained software pipeline fashion. A traditional software pipelined video decoder has fixed pipeline-stage partitions. The AVC/H.264 video decoder investigated in this paper dynamically assigns different stages of the video macroblock (MB) decoding tasks to different processor cores in order to maintain load balance among the processor cores. The pipeline partitioning policy is based on the queue levels of the inter-stage buffers. Experimental results show that, on average, the proposed dynamic pipeline-partitioning video decoder is 34% faster compared to a wavefront-based parallel video decoder.
AB - In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture allows the processor cores to cooperate efficiently in a fine-grained software pipeline fashion. A traditional software pipelined video decoder has fixed pipeline-stage partitions. The AVC/H.264 video decoder investigated in this paper dynamically assigns different stages of the video macroblock (MB) decoding tasks to different processor cores in order to maintain load balance among the processor cores. The pipeline partitioning policy is based on the queue levels of the inter-stage buffers. Experimental results show that, on average, the proposed dynamic pipeline-partitioning video decoder is 34% faster compared to a wavefront-based parallel video decoder.
KW - Symmetric stream multiprocessor (SSMP)
KW - dynamic load balance
KW - dynamic software pipeline
KW - parallel video decoding
UR - http://www.scopus.com/inward/record.url?scp=84955572789&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2015.7245716
DO - 10.1109/ASAP.2015.7245716
M3 - Conference contribution
AN - SCOPUS:84955572789
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 106
EP - 110
BT - Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015
Y2 - 27 July 2015 through 29 July 2015
ER -