Dynamic pipeline-partitioned video decoding on symmetric stream multiprocessors

Ming Ju Wu, Yan Ting Chen, Chun-Jen Tsai

研究成果: Conference contribution同行評審

摘要

In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture allows the processor cores to cooperate efficiently in a fine-grained software pipeline fashion. A traditional software pipelined video decoder has fixed pipeline-stage partitions. The AVC/H.264 video decoder investigated in this paper dynamically assigns different stages of the video macroblock (MB) decoding tasks to different processor cores in order to maintain load balance among the processor cores. The pipeline partitioning policy is based on the queue levels of the inter-stage buffers. Experimental results show that, on average, the proposed dynamic pipeline-partitioning video decoder is 34% faster compared to a wavefront-based parallel video decoder.

原文English
主出版物標題Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors
發行者Institute of Electrical and Electronics Engineers Inc.
頁面106-110
頁數5
ISBN(電子)9781479919246
DOIs
出版狀態Published - 8 9月 2015
事件26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 - Toronto, Canada
持續時間: 27 7月 201529 7月 2015

出版系列

名字Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
2015-September
ISSN(列印)1063-6862

Conference

Conference26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015
國家/地區Canada
城市Toronto
期間27/07/1529/07/15

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