摘要
A dynamic-floating-gate design is proposed to improve ESD robustness of the driving-current-programmable CMOS output buffers in a 0.35-μm CMOS cell library. Through suitable design to dynamically float the gates of the output NMOS/PMOS which are originally unused in a 2-mA output buffer, the ND-mode (PS-mode) ESD level of the 2-mA output buffer can be improved from the original 1.5 KV (1.0 KV) up to greater than 8 KV.
原文 | English |
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頁(從 - 到) | 216-219 |
頁數 | 4 |
期刊 | Proceedings - IEEE International Symposium on Circuits and Systems |
卷 | 2 |
DOIs | |
出版狀態 | Published - 1998 |
事件 | Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA 持續時間: 31 5月 1998 → 3 6月 1998 |