DVFS binning using machine-learning techniques

Keng Wei Chang, Chun Yang Huang, Szu Pang Mu, Jian Min Huang, Shi Hao Chen, Chia-Tso Chao

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

This paper presents a framework which can avoid the lengthy system test by utilizing machine-learning techniques to classify parts into different DVFS bins based on the results collected at CP and FT test only. The core machine-learning techniques in use are Bayesian linear regression for model fitting and stepwise regression for feature selection. Another method, called the incremental F-max-model search, is also presented to reduce the test time of collecting the required data for each training sample. The experiments are conducted based on 249 test chips of an industrial SoC. The experimental results demonstrate that our proposed framework can achieve a high accuracy ratio of placing a part into correct DVFS bin without placing any slower part into a faster DVFS bin. The experimental results also demonstrate that the incremental F-max-model search can save 45.1% and 52.6% of applications of the system-level test compared to the conventional median linear search and binary search, respectively.

原文English
主出版物標題Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面31-36
頁數6
ISBN(列印)9781538651803
DOIs
出版狀態Published - 11 9月 2018
事件2nd IEEE International Test Conference in Asia, ITC-Asia 2018 - Harbin, China
持續時間: 15 8月 201817 8月 2018

出版系列

名字Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018

Conference

Conference2nd IEEE International Test Conference in Asia, ITC-Asia 2018
國家/地區China
城市Harbin
期間15/08/1817/08/18

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