摘要
In this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.
原文 | English |
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頁(從 - 到) | K511-K516 |
期刊 | Materials Research Society Symposium - Proceedings |
卷 | 670 |
DOIs | |
出版狀態 | Published - 2001 |
事件 | Gate Stack and Silicide Issues in Silicon Processing II - San Francisco, CA, 美國 持續時間: 17 4月 2001 → 19 4月 2001 |