The Viterbi algorithm is widely applied for communication to derive the maximum-likelihood sequence estimates of transmitted data on channels with intersymbol interference (ISI) and/or coding. In this paper, we provide a VLSI design of Viterbi decoder for IS-54. Design features includes: switchable (2,1,5),(4,1,5) coder design, data inter-leaving, soft - decision. For hardware constrain, area efficiency is of great concern in handset design. Hence, optimized area efficient design is implemented-mented.
|出版狀態||Published - 18 10月 1996|
|事件||Proceedings of the 1996 7th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC'96. Part 3 (of 3) - Taipei, Taiwan|
持續時間: 15 10月 1996 → 18 10月 1996
|Conference||Proceedings of the 1996 7th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC'96. Part 3 (of 3)|
|期間||15/10/96 → 18/10/96|