TY - GEN
T1 - Dual mode channel equalizer design for MB-UWB and WiMAX systems
AU - Yeh, Po Lin
AU - Wen, Kuei-Ann
PY - 2010/12/1
Y1 - 2010/12/1
N2 - Dual-mode channel equalizer is proposed for IEEE 802.15.3.a (i.e. MB-UWB) and IEEE 802.16d (i.e. fixed WiMAX) OFDM systems. The proposed scheme comprises channel estimator (CE), frequency domain equalizer (FDE), phase error tracker (PET), and adaptive channel tracker to solve non-ideal effects, such as multi-path fading channel, AWGN, carrier frequency offset (CFO) and sampling clock offset (SCO). In MB-UWB system simulation, the proposed dual-mode channel equalizer contributes 2.06~9.7dB gain in SNR for 8% packet error rate (PER) specification in different transmission mode. On the other hand, it can also obtain 0.5~3.9 dB gain in SNR for 10-6 bite error rate (BER) requirement in WiMAX system. In hardware implementation, the architecture of proposed scheme uses two-parallelism to achieve high throughput rate up to 528M sample/s. Most of the functional blocks are reused to enhance the hardware efficiency. The design occupies only 130k equivalent gate count in UMC 0.18 μm technology.
AB - Dual-mode channel equalizer is proposed for IEEE 802.15.3.a (i.e. MB-UWB) and IEEE 802.16d (i.e. fixed WiMAX) OFDM systems. The proposed scheme comprises channel estimator (CE), frequency domain equalizer (FDE), phase error tracker (PET), and adaptive channel tracker to solve non-ideal effects, such as multi-path fading channel, AWGN, carrier frequency offset (CFO) and sampling clock offset (SCO). In MB-UWB system simulation, the proposed dual-mode channel equalizer contributes 2.06~9.7dB gain in SNR for 8% packet error rate (PER) specification in different transmission mode. On the other hand, it can also obtain 0.5~3.9 dB gain in SNR for 10-6 bite error rate (BER) requirement in WiMAX system. In hardware implementation, the architecture of proposed scheme uses two-parallelism to achieve high throughput rate up to 528M sample/s. Most of the functional blocks are reused to enhance the hardware efficiency. The design occupies only 130k equivalent gate count in UMC 0.18 μm technology.
UR - http://www.scopus.com/inward/record.url?scp=78651244159&partnerID=8YFLogxK
U2 - 10.1109/ISCIT.2010.5664912
DO - 10.1109/ISCIT.2010.5664912
M3 - Conference contribution
AN - SCOPUS:78651244159
SN - 9781424470105
T3 - ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
SP - 58
EP - 63
BT - ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
Y2 - 26 October 2010 through 29 October 2010
ER -