DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network

Jhen Gang Lin, Yu Guang Chen, Yun Wei Yang, Wei Tse Hung, Cheng Hong Tsai, De Shiun Fu, Mango Chia Tso Chao

研究成果: Conference contribution同行評審

摘要

Design Rule Checking (DRC) is one of the most important metrices in physical design procedure to evaluate quality of a detail route. The prediction of DRC violation (DRV) in the early stage can reduce the iterations of design procedure and improve the efficiency of the physical design closure. Several researchers have applied machine-learning techniques to predict the DRVs of a detail route at different design stages with various input features. In this paper, we proposed a machine learning model to predict DRVs with the information obtained after placement stage. Specifically, we build a ResNet-like CNN model to predict whether a DRV may occur in a targeted grid after detail route. Our features consist of not only quantified placement information but also layout-image features to take pin accessibility into account for better prediction result. Moreover, we apply an under-sampling technique to select critical training samples to improve the training efficiency. A series of experiments have been conducted and the results show that compared with previous works, our prediction result can outperform Fully Convolutional Network (FCN) based approaches.

原文English
主出版物標題GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
發行者Association for Computing Machinery
頁面313-319
頁數7
ISBN(電子)9798400701252
DOIs
出版狀態Published - 5 6月 2023
事件33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 - Knoxville, United States
持續時間: 5 6月 20237 6月 2023

出版系列

名字Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
國家/地區United States
城市Knoxville
期間5/06/237/06/23

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