Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach

Rong Jhe Lyu, Bo Shiuan Shie, Horng-Chih Lin, Pei-Wen Li, Tiao Yuan Huang

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9 × 107 and 4.2 × 107, superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.

原文English
文章編號7808990
頁(從 - 到)1069-1075
頁數7
期刊IEEE Transactions on Electron Devices
64
發行號3
DOIs
出版狀態Published - 1 3月 2017

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