Double noise coupling ΔΣ analogue-to-digital converter

Y. Jung; S. Lee; Chia-Hung Chen; G. C. Temes

doi:10.1049/el.2012.0272

Double noise coupling ΔΣ analogue-to-digital converter

Y. Jung^*, S. Lee, Chia-Hung Chen, G. C. Temes

^*此作品的通信作者

電機工程學系

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A novel ΔΣ analogue-to-digital (ADC) architecture is proposed for second-order noise shaping enhancement. The new architecture is less dependent on the opamp DC gain than the earlier ΔΣ ADC with second-order noise shaping enhancement. Also, the proposed architecture reduces the complexity of the clock generator and zero optimisation compared to the earlier one. A ΔΣ ADC using the new configuration was designed and simulated. The results verify the advantages of the proposed structure.

原文	English
頁（從 - 到）	557-558
頁數	2
期刊	Electronics Letters
卷	48
發行號	10
DOIs	https://doi.org/10.1049/el.2012.0272
出版狀態	Published - 10 5月 2012

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10.1049/el.2012.0272

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AB - A novel ΔΣ analogue-to-digital (ADC) architecture is proposed for second-order noise shaping enhancement. The new architecture is less dependent on the opamp DC gain than the earlier ΔΣ ADC with second-order noise shaping enhancement. Also, the proposed architecture reduces the complexity of the clock generator and zero optimisation compared to the earlier one. A ΔΣ ADC using the new configuration was designed and simulated. The results verify the advantages of the proposed structure.

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Double noise coupling ΔΣ analogue-to-digital converter

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