Distributed Sorting Architecture on Multiple FPGA

Yi Da Hsin, Yen Shi Kuo, Bo Cheng Lai

研究成果: Conference contribution同行評審

摘要

FPGA has demonstrated promising performance in high throughput data sorting. Data compression techniques are adopted to exploit the redundant information between subsequent values in a sorted dataset. However, the standalone FPGA design inhibits the scalability to handle the growing dataset. Moreover, previous data compression techniques in data sorting lack versatility to support various ranges of data. This paper proposes the design of a distributed sorting accelerator on multiple FPGAs and introduce a Configurable Compressed Array to handle the various data widths. The experimental results have shown that the proposed design attains 3.69x enhancement when compared to the previous design.

原文English
主出版物標題2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665409216
DOIs
出版狀態Published - 2022
事件2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, 台灣
持續時間: 18 4月 202221 4月 2022

出版系列

名字2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
國家/地區台灣
城市Hsinchu
期間18/04/2221/04/22

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