We have, for the first time, experimentally quantified random dopant distribution (RDD) induced Vt standard deviation up to 4OmV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V, variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
|頁（從 - 到）||208-209|
|期刊||Digest of Technical Papers - Symposium on VLSI Technology|
|出版狀態||Published - 12 6月 2007|
|事件||2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan|
持續時間: 12 6月 2007 → 14 6月 2007