Discrete dopant fluctuated 20nm/15nm-gate planar CMOS

We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V_t standard deviation up to 4OmV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V, variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.