Discrete dopant fluctuated 20nm/15nm-gate planar CMOS

Fu Liang Yang*, Jiunn Ren Hwang, Hung Ming Chen, Jeng Jung Shen, Shao Ming Yu, Yiming Li, Denny D. Tang


研究成果: Conference article同行評審

18 引文 斯高帕斯(Scopus)


We have, for the first time, experimentally quantified random dopant distribution (RDD) induced Vt standard deviation up to 4OmV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V, variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.

頁(從 - 到)208-209
期刊Digest of Technical Papers - Symposium on VLSI Technology
出版狀態Published - 12 6月 2007
事件2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
持續時間: 12 6月 200714 6月 2007


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