Dimensionality-aware redundant SIMT instruction elimination

Tsung Tai Yeh, Roland N. Green, Timothy G. Rogers

研究成果: Conference contribution同行評審

9 引文 斯高帕斯(Scopus)

摘要

In massively multithreaded architectures, redundantly executing the same instruction with the same operands in different threads is a significant source of inefficiency. This paper introduces Dimensionality-Aware Redundant SIMT Instruction Elimination (DARSIE), a non-speculative instruction skipping mechanism to reduce redundant operations in GPUs. DARSIE uses static markings from the compiler and information obtained at kernel launch time to skip redundant instructions before they are fetched, keeping them out of the pipeline. DARSIE exploits a new observation that there is significant redundancy across warp instructions in multi-dimensional threadblocks. For minimal area cost, DARSIE eliminates conditionally redundant instructions without any programmer intervention. On increasingly important 2D GPU applications, DARSIE reduces the number of instructions fetched and executed by 23% over contemporary GPUs. Not fetching these instructions results in a geometric mean of 30% performance improvement, while decreasing the energy consumed by 25%.

原文English
主出版物標題ASPLOS 2020 - 25th International Conference on Architectural Support for Programming Languages and Operating Systems
發行者Association for Computing Machinery
頁面1327-1340
頁數14
ISBN(電子)9781450371025
DOIs
出版狀態Published - 9 3月 2020
事件25th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2020 - Lausanne, Switzerland
持續時間: 16 3月 202020 3月 2020

出版系列

名字International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Conference

Conference25th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2020
國家/地區Switzerland
城市Lausanne
期間16/03/2020/03/20

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