Digitally programmable DC-DC voltage down converter

M. C. Lin, H. Y. Lin, C. L. Chen, Shyh-Jye Jou

研究成果: Conference contribution同行評審

摘要

This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-μm triple-metal CMOS process on 1000×1000 μm 2 core size. The simulation results show that it can convert +5 V input voltage to +2∼+5 V output voltage in the 50 μs settling time.

原文English
主出版物標題AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
發行者Institute of Electrical and Electronics Engineers Inc.
頁面367-370
頁數4
ISBN(列印)0780357051, 9780780357051
DOIs
出版狀態Published - 1 1月 1999
事件1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
持續時間: 23 8月 199925 8月 1999

出版系列

名字AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
國家/地區Korea, Republic of
城市Seoul
期間23/08/9925/08/99

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