Development of GaN HEMTs fabricated on silicon, silicon-on-insulator, and engineered substrates and the heterogeneous integration

Lung Hsing Hsu, Yung Yu Lai, Po Tsung Tu, Catherine Langpoklakpam, Ya Ting Chang, Yu Wen Huang, Wen Chung Lee, An Jye Tzou, Yuh Jen Cheng, Chun Hsiung Lin*, Hao-Chung Kuo, Edward Yi Chang

*此作品的通信作者

研究成果: Review article同行評審

11 引文 斯高帕斯(Scopus)

摘要

GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

原文American English
文章編號1159
頁(從 - 到)1-32
頁數32
期刊Micromachines
12
發行號10
DOIs
出版狀態Published - 10月 2021

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