TY - GEN
T1 - Design Space Exploration for Scaled FeFET Nonvolatile Memories
T2 - 6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022
AU - Liu, You Sheng
AU - Huang, Yuan Yu
AU - Su, Pin
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This work explores the design space for scaled FeFET NVMs using TCAD simulations considering the phase non-uniformity of ferroelectric. Our study suggests that, to meet the requirements including the memory window (MW) and the electric field across interfacial layer (EIL), high-k spacers can be a powerful aid for future scaled FeFETs. High-k spacers improve EIL during write operation, mean MW and the worst MW under a nonuniform phase distribution. More importantly, these improvements increase with the down-scaling of gate length.
AB - This work explores the design space for scaled FeFET NVMs using TCAD simulations considering the phase non-uniformity of ferroelectric. Our study suggests that, to meet the requirements including the memory window (MW) and the electric field across interfacial layer (EIL), high-k spacers can be a powerful aid for future scaled FeFETs. High-k spacers improve EIL during write operation, mean MW and the worst MW under a nonuniform phase distribution. More importantly, these improvements increase with the down-scaling of gate length.
UR - http://www.scopus.com/inward/record.url?scp=85133958985&partnerID=8YFLogxK
U2 - 10.1109/EDTM53872.2022.9798076
DO - 10.1109/EDTM53872.2022.9798076
M3 - Conference contribution
AN - SCOPUS:85133958985
T3 - 6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022
SP - 70
EP - 72
BT - 6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 6 March 2022 through 9 March 2022
ER -