Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes

Ming-Dou Ker*, T. Y. Chen

*此作品的通信作者

    研究成果: Conference article同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original ∼200V to become ≥ 3kV.

    原文English
    頁(從 - 到)IV758-IV761
    期刊Materials Research Society Symposium - Proceedings
    626
    DOIs
    出版狀態Published - 2001
    事件Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
    持續時間: 24 4月 200027 4月 2000

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