TY - GEN
T1 - Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes
AU - Ker, Ming-Dou
AU - Chen, Tung Yan
PY - 2001/12/1
Y1 - 2001/12/1
N2 - A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original /spl sim/200 V to become /spl ges/3 kV.
AB - A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original /spl sim/200 V to become /spl ges/3 kV.
UR - http://www.scopus.com/inward/record.url?scp=0142002808&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2001.922348
DO - 10.1109/ISCAS.2001.922348
M3 - Conference contribution
AN - SCOPUS:0142002808
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 758
EP - 761
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -