Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology

Ming-Dou Ker*, Hsin Chin Jiang, Chyh Yih Chang

*此作品的通信作者

    研究成果: Article同行評審

    11 引文 斯高帕斯(Scopus)

    摘要

    A new structure design of bond pad is proposed to reduce its parasitic capacitance in general CMOS processes without extra process modification. The proposed bond pad is constructed by connecting multilayer metals and inserting additional diffusion layers into the substrate below the metal layers. The metal layers except top metal layer are designed with special patterns, which have smaller area than that in the traditional bond pad. Both the additional diffusion layers and patterned metal layers are used to reduce the parasitic capacitance of bond pad. An experimental test chip has been designed and fabricated to investigate the reduction of parasitic capacitance of the bond pad. The bonding reliability tests on the fabricated bond pad, including the ball-shear and wire-pull tests, are also used to verify the bonding adhesion. The experimental results show that the proposed low-capacitance bond pad has a capacitance less than 50% of that in the traditional bond pad. The new proposed bond pads can also keep the same good bonding reliability as that of a traditional bond pad.

    原文English
    頁(從 - 到)2953-2956
    頁數4
    期刊IEEE Transactions on Electron Devices
    48
    發行號12
    DOIs
    出版狀態Published - 12月 2001

    指紋

    深入研究「Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology」主題。共同形成了獨特的指紋。

    引用此