Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process

Ming-Dou Ker; Wen Yi Chen; Kuo Chun Hsu

doi:10.1109/RELPHY.2005.1493165

Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process

Ming-Dou Ker^*, Wen Yi Chen, Kuo Chun Hsu

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

6 引文斯高帕斯（Scopus）

摘要

A new power-rail ESD clamp circuit in a 130-nm 1-V/2.5-V CMOS process for application in 3.3-V mixed-voltage I/O interface is proposed. The devices used in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage NMOS/PMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.

原文	English
主出版物標題	2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
頁面	606-607
頁數	2
DOIs	https://doi.org/10.1109/RELPHY.2005.1493165
出版狀態	Published - 2005
事件	2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual - San Jose, CA, United States 持續時間: 17 4月 2005 → 21 4月 2005

出版系列

名字	IEEE International Reliability Physics Symposium Proceedings
ISSN（列印）	1541-7026

Conference

Conference	2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
國家/地區	United States
城市	San Jose, CA
期間	17/04/05 → 21/04/05

存取文件

10.1109/RELPHY.2005.1493165

其它文件與鏈接

Link to publication in Scopus

引用此

Ker, M.-D., Chen, W. Y., & Hsu, K. C. (2005). Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process. 於 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual (頁 606-607). (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/RELPHY.2005.1493165

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title = "Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process",

abstract = "A new power-rail ESD clamp circuit in a 130-nm 1-V/2.5-V CMOS process for application in 3.3-V mixed-voltage I/O interface is proposed. The devices used in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage NMOS/PMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.",

author = "Ming-Dou Ker and Chen, {Wen Yi} and Hsu, {Kuo Chun}",

year = "2005",

doi = "10.1109/RELPHY.2005.1493165",

language = "English",

isbn = "0780388038",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "606--607",

booktitle = "2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual",

note = "2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual ; Conference date: 17-04-2005 Through 21-04-2005",

}

Ker, M-D, Chen, WY & Hsu, KC 2005, Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process. 於 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual. IEEE International Reliability Physics Symposium Proceedings, 頁 606-607, 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual, San Jose, CA, United States, 17/04/05. https://doi.org/10.1109/RELPHY.2005.1493165

Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process. / Ker, Ming-Dou; Chen, Wen Yi; Hsu, Kuo Chun.
2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual. 2005. p. 606-607 (IEEE International Reliability Physics Symposium Proceedings).

研究成果: Conference contribution › 同行評審

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AU - Ker, Ming-Dou

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N2 - A new power-rail ESD clamp circuit in a 130-nm 1-V/2.5-V CMOS process for application in 3.3-V mixed-voltage I/O interface is proposed. The devices used in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage NMOS/PMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.

AB - A new power-rail ESD clamp circuit in a 130-nm 1-V/2.5-V CMOS process for application in 3.3-V mixed-voltage I/O interface is proposed. The devices used in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage NMOS/PMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.

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M3 - Conference contribution

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BT - 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual

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Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process

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