This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 7 9月 2004|
|事件||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
持續時間: 23 5月 2004 → 26 5月 2004