Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in A 0.13-μM CMOS technology

Che Hao Chuang*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Conference article同行評審

    32 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.

    原文English
    頁(從 - 到)II577-II580
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    2
    DOIs
    出版狀態Published - 2004
    事件2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
    持續時間: 23 5月 200426 5月 2004

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