Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in A 0.13-μM CMOS technology

Che Hao Chuang; Ming-Dou Ker

doi:10.1109/ISCAS.2004.1329337

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in A 0.13-μM CMOS technology

Che Hao Chuang^*, Ming-Dou Ker

^*此作品的通信作者

研究成果: Conference article › 同行評審

31 引文斯高帕斯（Scopus）

摘要

This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.

原文	English
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	2
DOIs	https://doi.org/10.1109/ISCAS.2004.1329337
出版狀態	Published - 7 9月 2004
事件	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada 持續時間: 23 5月 2004 → 26 5月 2004

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10.1109/ISCAS.2004.1329337

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title = "Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in A 0.13-μM CMOS technology",

abstract = "This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.",

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doi = "10.1109/ISCAS.2004.1329337",

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AU - Chuang, Che Hao

AU - Ker, Ming-Dou

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Y1 - 2004/9/7

N2 - This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.

AB - This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.

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U2 - 10.1109/ISCAS.2004.1329337

DO - 10.1109/ISCAS.2004.1329337

M3 - Conference article

AN - SCOPUS:4344701276

SN - 0271-4310

VL - 2

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in A 0.13-μM CMOS technology

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