Design on Mixed-Voltage I/O buffer with blocking NMOS and dynamic Gate-Controlled circuit for High-Voltage-Tolerant applications

Ming-Dou Ker, Shih Lun Chen, Chia Sheng Tsai

    研究成果: Conference article同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltagetolerant applications is proposed. The new proposed I/O buffer can receive the input signals with the voltage swing twice as high as the normal power supply voltage (VDD), which has been fabricated in a 0.25-μm CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-μm (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.

    原文English
    文章編號1464973
    頁(從 - 到)1859-1862
    頁數4
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    DOIs
    出版狀態Published - 2005
    事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    持續時間: 23 5月 200526 5月 2005

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