Design on ESD protection circuit with very low and constant input capacitance

Tung Yang Chen, Ming-Dou Ker

    研究成果: Conference contribution同行評審

    5 引文 斯高帕斯(Scopus)

    摘要

    Effective on-chip ESD design to solve the ESD protection challenge on the analog pins for high-frequency or current-mode applications is studied. The device dimension of ESD clamp devices in analog ESD protection circuit can be reduced to have a much small input capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD level. To find the optimized device dimensions and layout spacings on ESD clamp devices, a design model is developed to keep the input capacitance as constant as possible (within 1% variation).

    原文English
    主出版物標題Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001
    發行者IEEE Computer Society
    頁面247-248
    頁數2
    ISBN(電子)0769510256
    DOIs
    出版狀態Published - 28 3月 2001
    事件2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 - San Jose, United States
    持續時間: 26 3月 200128 3月 2001

    出版系列

    名字Proceedings - International Symposium on Quality Electronic Design, ISQED
    2001-January
    ISSN(列印)1948-3287
    ISSN(電子)1948-3295

    Conference

    Conference2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001
    國家/地區United States
    城市San Jose
    期間26/03/0128/03/01

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