TY - CHAP
T1 - Design of power-rail ESD clamp circuits with gate-leakage consideration in nanoscale CMOS technology
AU - Ker, Ming-Dou
AU - Yeh, Chih Ting
N1 - Publisher Copyright:
© 2016 by Taylor and Francis Group, LLC.
PY - 2017/1/1
Y1 - 2017/1/1
N2 - Electrostatic discharge (ESD) phenomenon is a charge flow when two objects with different voltage potentials reach contact. Such ESD events can cause serious damage to the integrated circuit (IC) products, during assembly, testing, and manufacturing. To protect the IC products with the required ESD specifications, typically such as 2 kV in human body model (HBM) [1] and 200 V in machine model (MM) [2], the whole-chip ESD protection scheme formed with the power-rail ESD clamp circuit had been often used in the modern IC products [3]. As shown in Figure 5.1, the power-rail ESD clamp circuit is a vital element for ESD protection under different ESD stress modes. The ESD stress modes include V dd-to-V ss (or V ss-to-V dd) ESD stress between the rails, as well as the positive-to-V ss (PS) mode, negative-to-V ss (NS) mode, positive-to-V dd (PD) mode, and negative-to-V dd (ND) mode, from input/output (I/O) to V dd/V ss. Therefore, the power-rail ESD clamp circuit must provide low-impedance discharging path under ESD events but keep in off-state with standby leakage current as low as possible under normal circuit operation conditions.
AB - Electrostatic discharge (ESD) phenomenon is a charge flow when two objects with different voltage potentials reach contact. Such ESD events can cause serious damage to the integrated circuit (IC) products, during assembly, testing, and manufacturing. To protect the IC products with the required ESD specifications, typically such as 2 kV in human body model (HBM) [1] and 200 V in machine model (MM) [2], the whole-chip ESD protection scheme formed with the power-rail ESD clamp circuit had been often used in the modern IC products [3]. As shown in Figure 5.1, the power-rail ESD clamp circuit is a vital element for ESD protection under different ESD stress modes. The ESD stress modes include V dd-to-V ss (or V ss-to-V dd) ESD stress between the rails, as well as the positive-to-V ss (PS) mode, negative-to-V ss (NS) mode, positive-to-V dd (PD) mode, and negative-to-V dd (ND) mode, from input/output (I/O) to V dd/V ss. Therefore, the power-rail ESD clamp circuit must provide low-impedance discharging path under ESD events but keep in off-state with standby leakage current as low as possible under normal circuit operation conditions.
UR - http://www.scopus.com/inward/record.url?scp=85052766256&partnerID=8YFLogxK
U2 - 10.1201/b18976
DO - 10.1201/b18976
M3 - Chapter
AN - SCOPUS:85052766256
SN - 9781482255881
SP - 67
EP - 86
BT - Electrostatic Discharge Protection
PB - CRC Press
ER -