摘要
A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication.
原文 | English |
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文章編號 | 1464919 |
頁(從 - 到) | 1642-1645 |
頁數 | 4 |
期刊 | Proceedings - IEEE International Symposium on Circuits and Systems |
DOIs | |
出版狀態 | Published - 23 5月 2005 |
事件 | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, 日本 持續時間: 23 5月 2005 → 26 5月 2005 |