Design of mixed-voltage crystal oscillator circuit in low-voltage CMOS technology

Ming-Dou Ker*, Hung Tai Liao

*此作品的通信作者

    研究成果: Conference article同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to support a higher operating speed under a lower power supply (1×VDD). However, the board-level voltage levels could be still in a higher voltage levels (2×VDD, or even more) for compatible to some earlier interface specifications in a microelectronics system. The I/O interface circuits have been designed with consideration on the gate-oxide reliability in such mixed-voltage applications. In this work, a new mixed-voltage crystal oscillator circuit realized with low-voltage CMOS devices is proposed without suffering the gate-oxide reliability issue. The proposed mixed-voltage crystal oscillator circuit, which is one of the key I/O cells in a cell library, has been designed and verified in a 90-nm 1-V CMOS process to serve 1/1.8-V mixed-voltage interface applications.

    原文English
    文章編號4252836
    頁(從 - 到)1121-1124
    頁數4
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    DOIs
    出版狀態Published - 27 9月 2007
    事件2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
    持續時間: 27 5月 200730 5月 2007

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