TY - GEN
T1 - Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process
AU - Chiu, Po Yen
AU - Ker, Ming-Dou
PY - 2011/6/24
Y1 - 2011/6/24
N2 - A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.
AB - A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.
UR - http://www.scopus.com/inward/record.url?scp=79959333302&partnerID=8YFLogxK
U2 - 10.1109/ICICDT.2011.5783185
DO - 10.1109/ICICDT.2011.5783185
M3 - Conference contribution
AN - SCOPUS:79959333302
SN - 9781424490202
T3 - 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
BT - 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
T2 - 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
Y2 - 2 May 2011 through 4 May 2011
ER -