Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

Po Yen Chiu*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Conference contribution同行評審

    10 引文 斯高帕斯(Scopus)

    摘要

    A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.

    原文English
    主出版物標題2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
    DOIs
    出版狀態Published - 24 6月 2011
    事件2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011 - Kaohsiung, Taiwan
    持續時間: 2 5月 20114 5月 2011

    出版系列

    名字2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

    Conference

    Conference2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
    國家/地區Taiwan
    城市Kaohsiung
    期間2/05/114/05/11

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