TY - JOUR
T1 - Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits
AU - Ker, Ming-Dou
AU - Jiang, Hsin Chin
AU - Chang, Chyh Yih
PY - 2000/9/13
Y1 - 2000/9/13
N2 - A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.
AB - A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.
UR - http://www.scopus.com/inward/record.url?scp=0033696592&partnerID=8YFLogxK
U2 - 10.1109/ASIC.2000.880752
DO - 10.1109/ASIC.2000.880752
M3 - Conference article
AN - SCOPUS:0033696592
SN - 1063-0988
SP - 293
EP - 296
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
M1 - 880752
T2 - Proceedings of the 13th Annual IEEE International ASIC/SOC Conference
Y2 - 13 September 2000 through 16 September 2000
ER -