Design of instruction stream buffer with trace support for X86 processors

Jih Ching Chiu*, I. Huan Huang, Chung-Ping Chung


研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)


The potential performance of superscalar microprocessors can be exploited only when fed with sufficient instruction bandwidth. The front-end units, the instruction stream buffer and the fetcher, are the key elements achieving this goal. In most current processors, instruction stream buffers cannot support the instruction sequence beyond a basic block. The fetch rates are constrained by the branch barriers. In x86 processors, the split-line instruction problem worsens this constrain. We propose a design to improve instruction stream buffer performance by coupling it with BTB to support trace prediction. According to the simulation results of such an instruction stream buffer, the maximum fetch bandwidth can reach 8.42 x86 instructions per cycle. Furthermore, we suggest that the instruction stream buffer consist of two 64-bytes entries. Compared with other existing designs, this instruction stream buffer can improve performance by 90% over current x86 processor instruction fetching on average.

出版狀態Published - 2000
事件2000 International Conference on Computer Design - Austin, TX, USA
持續時間: 17 9月 200020 9月 2000


Conference2000 International Conference on Computer Design
城市Austin, TX, USA


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