TY - JOUR
T1 - Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes
AU - Chang, Rong Kun
AU - Ker, Ming Dou
PY - 2020/1
Y1 - 2020/1
N2 - In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of-6 V has been proposed and verified in a 0.18-μ m 3.3-V CMOS process. The proposed circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this-6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of 400μ m can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of 5.4 nA at room temperature under the circuit operating condition with-6-V supply voltage.
AB - In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of-6 V has been proposed and verified in a 0.18-μ m 3.3-V CMOS process. The proposed circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this-6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of 400μ m can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of 5.4 nA at room temperature under the circuit operating condition with-6-V supply voltage.
KW - Electrostatic discharge (ESD)
KW - high-voltage-tolerant ESD clamp circuit
KW - negative voltage supply
KW - power-rail ESD clamp circuit
UR - http://www.scopus.com/inward/record.url?scp=85077817367&partnerID=8YFLogxK
U2 - 10.1109/TED.2019.2954754
DO - 10.1109/TED.2019.2954754
M3 - Article
AN - SCOPUS:85077817367
SN - 0018-9383
VL - 67
SP - 40
EP - 46
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 1
M1 - 8933351
ER -