Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes

Ming-Dou Ker*, Chang Tzu Wang, Tien Hao Tang, Kuan Cheng Su

*此作品的通信作者

    研究成果: Conference contribution同行評審

    6 引文 斯高帕斯(Scopus)

    摘要

    A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1×VDD devices for 3×VDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-μm CMOS process with only 1.2-V devices.

    原文English
    主出版物標題2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
    頁面594-595
    頁數2
    DOIs
    出版狀態Published - 25 9月 2007
    事件45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, 美國
    持續時間: 15 4月 200719 4月 2007

    出版系列

    名字Annual Proceedings - Reliability Physics (Symposium)
    ISSN(列印)0099-9512

    Conference

    Conference45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
    國家/地區美國
    城市Phoenix, AZ
    期間15/04/0719/04/07

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