TY - GEN
T1 - Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator
AU - Luo, Zhicong
AU - Ker, Ming-Dou
PY - 2016/10/20
Y1 - 2016/10/20
N2 - A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-μm CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (VDD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the coupling capacitors and the cross-coupled transistor pairs. Electrical overstress and the gate-oxide reliability issues can be fully eliminated because all transistors in the proposed level shifter are operating within the safe voltage range.
AB - A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-μm CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (VDD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the coupling capacitors and the cross-coupled transistor pairs. Electrical overstress and the gate-oxide reliability issues can be fully eliminated because all transistors in the proposed level shifter are operating within the safe voltage range.
UR - http://www.scopus.com/inward/record.url?scp=84998705807&partnerID=8YFLogxK
U2 - 10.1109/NEWCAS.2016.7604772
DO - 10.1109/NEWCAS.2016.7604772
M3 - Conference contribution
AN - SCOPUS:84998705807
T3 - 14th IEEE International NEWCAS Conference, NEWCAS 2016
BT - 14th IEEE International NEWCAS Conference, NEWCAS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th IEEE International NEWCAS Conference, NEWCAS 2016
Y2 - 26 June 2016 through 29 June 2016
ER -