Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology

Hun Hsien Chang*, Ming-Dou Ker, Jiin Chuan Wu

*此作品的通信作者

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the different circuit connections on the output devices. By adding suitable time delay to dynamically float the gates of the output NMOS/PMOS devices which are originally unused in the output buffer, the human-body-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-μm bulk CMOS process.

原文English
頁(從 - 到)375-393
頁數19
期刊Solid-State Electronics
43
發行號2
DOIs
出版狀態Published - 1 1月 1999

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