Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Keyphrases

• Power Rail 100%
• Clamp Circuit 100%
• CMOS ASIC 100%
• CMOS Process 50%
• CMOS Technology 50%
• Silicon Area 50%
• NMOS Device 50%
• Layout Area 50%
• Device Structure 50%
• ESD Robustness 50%
• Submicron CMOS 50%
• Protection Device 50%
• Power-rail ESD Clamp Circuit 50%
• Unit Layout 50%

Engineering

• Application Specific Integrated Circuit 100%
• Power Rail 100%
• Experimental Result 50%
• Bipolar Transistor 50%
• Device Structure 50%
• Protection Device 50%

Material Science

• Electronic Circuit 100%
• Silicon 33%
• Bipolar Transistor 33%