Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu

*此作品的通信作者

研究成果: Conference article同行評審

15 引文 斯高帕斯(Scopus)

摘要

Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.

原文English
頁(從 - 到)287-290
頁數4
期刊Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
出版狀態Published - 1997
事件Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
持續時間: 7 9月 199710 9月 1997

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