Design of CMOS analog cells for low-voltage VLSI

Chung-Chih Hung*, Changku Hwang, Kari Halonen, Veikko Porra, Mohammed Ismail

*此作品的通信作者

研究成果: Paper同行評審

摘要

In this paper, two CMOS analog signal processing circuits which could find wide use in low-voltage VLSI applications are presented. The two circuits include a voltage-to-current converter (V-I converter) and a multiplier. Both of the circuits can operate from rail to rail with a power supply of 3V. They were fabricated in a 2μm N-well double-poly CMOS process by MOSIS. In either of the circuits, an N-type circuit cell is connected in parallel with its P-type counterpart to achieve common-mode rail-to-rail operation. For the V-I converter, a nominal value of a 200μS transconductance with a tuning range of 0.5 to 2 is obtained when the input signal swing is 1 VPP. For the analog multiplier, it is realized by a parallel connection of the two V-I converters. Both of the input signal swings of the multiplier are measured as 1VPP and 1.6VPP, respectively.

原文English
頁面15-18
頁數4
DOIs
出版狀態Published - 1 12月 1996
事件Proceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3) - Ames, IA, USA
持續時間: 18 8月 199621 8月 1996

Conference

ConferenceProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3)
城市Ames, IA, USA
期間18/08/9621/08/96

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