Design of application specific throughput processor for matrix operations

Ping Ju Wu, Chien Yu Lin, Bo-Cheng Lai

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

In modern computation routines, matrix operations are broadly used in many scientific realms, ranging from high performance supercomputers to resource constrained embedded devices. Previous studies have revealed that the computation efficiency of matrix operations is significantly determined by the data accesses behavior of the computation platform. This paper introduces an integrated multicore system, including software stacks and hardware modules that can accelerate matrix operations and reduce data access overhead. With the proposed hardware module, the performance of our multicore embedded platform can improve up to 24.09%. Besides the hardware design, we also develop a framework that can facilitate the prototyping of embedded system designs, including functional verification of hardware modules as well as co-simulation with high level OpenCL language.

原文English
主出版物標題Proceedings - 2015 18th International Conference on Network-Based Information Systems, NBiS 2015
編輯Leonard Barolli, Makoto Takizawa, Fatos Xhafa, Hui-Huang Hsu, Tomoya Enokido
發行者Institute of Electrical and Electronics Engineers Inc.
頁面324-331
頁數8
ISBN(電子)9781479999422
DOIs
出版狀態Published - 9 12月 2015
事件18th International Conference on Network-Based Information Systems, NBiS 2015 - Taipei, Taiwan
持續時間: 2 9月 20154 9月 2015

出版系列

名字Proceedings - 2015 18th International Conference on Network-Based Information Systems, NBiS 2015

Conference

Conference18th International Conference on Network-Based Information Systems, NBiS 2015
國家/地區Taiwan
城市Taipei
期間2/09/154/09/15

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