Design of an all-digital LVDS driver

Hungwen Lu; Hsin Wen Wang; Chau-Chin Su; Chien-Nan Liu

doi:10.1109/TCSI.2008.2008279

Design of an all-digital LVDS driver

Hungwen Lu^*, Hsin Wen Wang, Chau-Chin Su, Chien-Nan Liu

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13 引文斯高帕斯（Scopus）

摘要

This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-μm 1P6M CMOS process with a core area of 0.072 mm². At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/ bit.

原文	English
頁（從 - 到）	1635-1644
頁數	10
期刊	IEEE Transactions on Circuits and Systems I: Regular Papers
卷	56
發行號	8
DOIs	https://doi.org/10.1109/TCSI.2008.2008279
出版狀態	Published - 2009

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10.1109/TCSI.2008.2008279

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AU - Su, Chau-Chin

AU - Liu, Chien-Nan

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AB - This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-μm 1P6M CMOS process with a core area of 0.072 mm2. At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/ bit.

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KW - Simultaneous switching noise (SSN)

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Design of an all-digital LVDS driver

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