Design of a systolic array system for linear state equations.

Shyh-Jye Jou*, Chein Wei Jen, Wen Zen Shen

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

The dependence-graph (DG) approach is extended and applied to the systematic design of a systolic array system. Two DGs that represent two different but data-dependent process algorithms are first linked together. Tag bits are added onto index nodes in this linked DG and used to indicate the different functions to be executed on single processor element. By applying the conventional time-scheduling and node-assignment procedures to this tagged DG, the interfacing communication problem of a systolic array system can be solved and the optimal latency can be easily obtained. Using this method, an optimal linear-state solver has been designed.

原文English
主出版物標題Proc Int Conf on Systolic Arrays
發行者Publ by IEEE
頁面275-284
頁數10
ISBN(列印)0818688602
DOIs
出版狀態Published - 1988

出版系列

名字Proc Int Conf on Systolic Arrays

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