Design of a multimode QC-LDPC decoder based on shift-routing network

Chih Hao Liu*, Chien Ching Lin, Shau Wei Yen, Chih Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar Sun Hsu, Shyh-Jye Jou

*此作品的通信作者

    研究成果: Article同行評審

    29 引文 斯高帕斯(Scopus)

    摘要

    A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22-mm2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.

    原文English
    頁(從 - 到)734-738
    頁數5
    期刊IEEE Transactions on Circuits and Systems I: Regular Papers
    56
    發行號9
    DOIs
    出版狀態Published - 2009

    指紋

    深入研究「Design of a multimode QC-LDPC decoder based on shift-routing network」主題。共同形成了獨特的指紋。

    引用此