Design of a lower-error fixed-width multiplier for speech processing application

Lan-Da Van; Shuenn Shyang Wang; Shing Tenqchen; Wu Shiung Feng; Bor Shenn Jeng

doi:10.1109/ISCAS.1999.778802

Design of a lower-error fixed-width multiplier for speech processing application

Lan-Da Van^*, Shuenn Shyang Wang, Shing Tenqchen, Wu Shiung Feng, Bor Shenn Jeng

^*此作品的通信作者

資訊科學與工程研究所

研究成果: Conference contribution › 同行評審

9 引文斯高帕斯（Scopus）

摘要

A lower-error and lower-variance n × n multiplier is suitably proposed for VLSI design. Considering next lower significant stage in P_n-1 column and useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors as shown in given tables and figures.

原文	English
主出版物標題	Proceedings - IEEE International Symposium on Circuits and Systems
發行者	IEEE
頁面	130-133
ISBN（列印）	0780354710
DOIs	https://doi.org/10.1109/ISCAS.1999.778802
出版狀態	Published - 1 1月 1999
事件	Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA 持續時間: 30 5月 1999 → 2 6月 1999

出版系列

名字	Proceedings - IEEE International Symposium on Circuits and Systems
卷	3
ISSN（列印）	0271-4310

Conference

Conference	Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
城市	Orlando, FL, USA
期間	30/05/99 → 2/06/99

存取文件

10.1109/ISCAS.1999.778802

其它文件與鏈接

Link to publication in Scopus

引用此

@inproceedings{35339ebdffd9430f9b360e8804d39e7b,

title = "Design of a lower-error fixed-width multiplier for speech processing application",

abstract = "A lower-error and lower-variance n × n multiplier is suitably proposed for VLSI design. Considering next lower significant stage in Pn-1 column and useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors as shown in given tables and figures.",

author = "Lan-Da Van and Wang, {Shuenn Shyang} and Shing Tenqchen and Feng, {Wu Shiung} and Jeng, {Bor Shenn}",

year = "1999",

month = jan,

day = "1",

doi = "10.1109/ISCAS.1999.778802",

language = "English",

isbn = "0780354710",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

pages = "130--133",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

note = "Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 ; Conference date: 30-05-1999 Through 02-06-1999",

}

Van, L-D, Wang, SS, Tenqchen, S, Feng, WS & Jeng, BS 1999, Design of a lower-error fixed-width multiplier for speech processing application. 於 Proceedings - IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, 卷 3, IEEE, 頁 130-133, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99, Orlando, FL, USA, 30/05/99. https://doi.org/10.1109/ISCAS.1999.778802

TY - GEN

T1 - Design of a lower-error fixed-width multiplier for speech processing application

AU - Van, Lan-Da

AU - Wang, Shuenn Shyang

AU - Tenqchen, Shing

AU - Feng, Wu Shiung

AU - Jeng, Bor Shenn

PY - 1999/1/1

Y1 - 1999/1/1

N2 - A lower-error and lower-variance n × n multiplier is suitably proposed for VLSI design. Considering next lower significant stage in Pn-1 column and useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors as shown in given tables and figures.

AB - A lower-error and lower-variance n × n multiplier is suitably proposed for VLSI design. Considering next lower significant stage in Pn-1 column and useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors as shown in given tables and figures.

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U2 - 10.1109/ISCAS.1999.778802

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M3 - Conference contribution

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99

Y2 - 30 May 1999 through 2 June 1999

ER -

Design of a lower-error fixed-width multiplier for speech processing application

摘要

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Conference

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指紋

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