TY - GEN
T1 - Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor
AU - Lin, Hong Ke
AU - Lin, Pin Han
AU - Liu, Chih-Wei
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/8
Y1 - 2020/8
N2 - In recent years, many popular technologies require a highthroughput ultra-long FFT processor, such as the OFDM and FMCW radars. In order to get high throughput, we use the MDC architecture to design the FFT processor. In addition, we added the 2-epoch architecture [1] to reduce the area of FIFOs in the MDC processor. Since the input to the MDC FFT is not in natural order, we need to design a reorder circuit. We proposed a data-scheduling algorithm that allows the reorder circuit to use the least number of memory banks to achieve area reduction. Furthermore, we proposed a twiddle-factorgenerator circuit for the 2-epoch architecture. It can effectively reduce the number of twiddle factors that need to be stored. We designed different specifications of FFT processors using the method described in this paper, and then synthesized using the TSMC 90 nm CMOS technology high-Vt standard cell library. Our processors can operate above 450MHz and the throughput is P\cdot R, where P is the parallelism of hardware and the R is the operating frequency.
AB - In recent years, many popular technologies require a highthroughput ultra-long FFT processor, such as the OFDM and FMCW radars. In order to get high throughput, we use the MDC architecture to design the FFT processor. In addition, we added the 2-epoch architecture [1] to reduce the area of FIFOs in the MDC processor. Since the input to the MDC FFT is not in natural order, we need to design a reorder circuit. We proposed a data-scheduling algorithm that allows the reorder circuit to use the least number of memory banks to achieve area reduction. Furthermore, we proposed a twiddle-factorgenerator circuit for the 2-epoch architecture. It can effectively reduce the number of twiddle factors that need to be stored. We designed different specifications of FFT processors using the method described in this paper, and then synthesized using the TSMC 90 nm CMOS technology high-Vt standard cell library. Our processors can operate above 450MHz and the throughput is P\cdot R, where P is the parallelism of hardware and the R is the operating frequency.
UR - https://www.scopus.com/pages/publications/85093666109
U2 - 10.1109/VLSI-DAT49148.2020.9196280
DO - 10.1109/VLSI-DAT49148.2020.9196280
M3 - Conference contribution
T3 - 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
BT - 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
Y2 - 10 August 2020 through 13 August 2020
ER -