@inproceedings{3c758d205a4e4630b425d908ca6d5820,
title = "Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit against False Trigger during Fast Power-ON Events",
abstract = "A new 2xVDD-tolerant power-rail ESD clamp circuit with voltage-level detection realized by 1xVDD devices is proposed against false trigger issue under fast power-on condition. All the 1xVDD devices in the proposed 2xVDD-tolerant ESD circuit are safely operated without gate oxide reliability issue. The proposed ESD clamp circuit has been implemented and verified in a 0.18-μm CMOS technology with 1.8-V devices. The experimental results have confirmed that the proposed ESD clamp circuit sustains a good HBM ESD level of 5.25kV and high immunity against false trigger issue under fast power-on condition. Moreover, polysilicon diodes are also verified to further reduce the stand-by leakage current of the proposed 2xVDD-tolerant power-rail ESD clamp circuit. ",
keywords = "2xVDD-tolerant, ESD, false trigger issue, polysilicon diodes, voltage detection",
author = "Huang, {Han Sheng} and Ker, {Ming Dou}",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 ; Conference date: 19-04-2021 Through 22-04-2021",
year = "2021",
month = apr,
day = "19",
doi = "10.1109/VLSI-DAT52063.2021.9427327",
language = "English",
series = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",
address = "美國",
}