TY - GEN
T1 - Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology
AU - Chiu, Po Yen
AU - Ker, Ming-Dou
PY - 2013
Y1 - 2013
N2 - The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×V DD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD voltage environment without suffering the gate-oxide reliability issue.
AB - The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×V DD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD voltage environment without suffering the gate-oxide reliability issue.
UR - http://www.scopus.com/inward/record.url?scp=84898434965&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2013.6749656
DO - 10.1109/SOCC.2013.6749656
M3 - Conference contribution
AN - SCOPUS:84898434965
SN - 9781479911660
T3 - International System on Chip Conference
SP - 33
EP - 36
BT - Proceedings - IEEE 26th International SOC Conference, SOCC 2013
PB - IEEE Computer Society
T2 - 26th IEEE International System-on-Chip Conference, SOCC 2013
Y2 - 4 September 2013 through 6 September 2013
ER -