摘要
This paper investigates the potential of complementary ferroelectric FETs (CFeFETs) to enable nonvolatile SRAM (nv-SRAM) and logic-in-memory applications. CFeFET consisting of stacking n-type FeFET and p-type FeFET, and the Ron/Roff ratio of the complementary paths in a CFeFET is larger than 106. For enhancing the feasibility of CFeFET, 4T CFeFET nv-SRAM with separated R/W ports is proposed and evaluated. Moreover, we further demonstrated several logic-in-memory applications using CFeFETs, including content addressable memory (CAM), lossless digital computation-in-memory circuits (D-CIM) and hyperdimensional computing (HDC). The simulation results of these circuits show CFeFETs achieving superior power-performance-area (PPA) compared to current approaches. The energy efficiency of D-CIM and HDC can be achieved above 1000 TOPS/W.
| 原文 | English |
|---|---|
| 主出版物標題 | Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025 |
| 發行者 | Institute of Electrical and Electronics Engineers Inc. |
| ISBN(電子) | 9798331589073 |
| DOIs | |
| 出版狀態 | Published - 2025 |
| 事件 | 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025 - Busan, 韓國 持續時間: 12 10月 2025 → 15 10月 2025 |
出版系列
| 名字 | Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025 |
|---|
Conference
| Conference | 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025 |
|---|---|
| 國家/地區 | 韓國 |
| 城市 | Busan |
| 期間 | 12/10/25 → 15/10/25 |
UN SDG
此研究成果有助於以下永續發展目標
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SDG 7 經濟實惠的清潔能源
指紋
深入研究「Design Navigation and Exploration of Complementary Ferroelectric FET (CFeFET) for Next-Generation CFET-based Nonvolatile SRAM and Logic-in-Memory Applications」主題。共同形成了獨特的指紋。引用此
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