Design, implementation, and performance evaluation of an earliest-deadline-first packet scheduling scheme in P4 hardware switches

Keyphrases

• Design Evaluation 100%
• Performance Evaluation 100%
• Implementation Evaluation 100%
• Destination Node 100%
• Hardware Switch 100%
• Packet Scheduling 100%
• Real-time Packet 100%
• Earliest Deadline First 100%
• Latency 33%
• Switch-off 33%
• Congestion 33%
• Priority Queue 33%
• Source Node 33%
• Real-time Traffic 33%
• Virtual Reality 33%
• Time Application 33%
• Videoconferencing 33%
• Queuing Delay 33%
• Nuclear Plant 33%
• Plant Control 33%
• Multiple Switches 33%
• High-speed Train Control 33%
• Deadline Miss 33%

Computer Science

• Design Implementation 100%
• Scheduling Scheme 100%
• Performance Evaluation 100%
• Destination Node 100%
• Packet Scheduling 100%
• Computer Hardware 100%
• Experimental Result 33%
• Miss Rate 33%
• Virtual Reality 33%
• Real-Time Application 33%
• Videoconferencing 33%
• Queueing Delay 33%