摘要
We report a novel design of amorphous silicon gate (ASG) driver circuit with not only low output noises but also improved reliability. The ASG circuits are made of thin-film transistors (TFTs) and integrated in the substrate glass. Unlike the most traditional ASG circuits, the proposed pull-down signals are complementary with lower frequency to discharge the critical nodes in the proposed circuit. The new pull-down signals are created to discharge each two adjacent stage circuits. By inputting two controlled pulse signals, the prospective pull-down signals can be created eventually in the circuit. To simulate the real driving conditions, a string of a resistance (1.24 {\hbox{k}}\Omega) and a capacitance (85.5 pF) are connected to each output as loading. By probing the output pads of the real circuit sample, the output characteristics can practicably be measured. In particular, the output ripples can be suppressed to 0.28 V. Moreover, the measured threshold voltage ({\rm V}-{\rm th}) shift with two stressing signals at different frequencies reveals the significant difference. The measured {\rm V}\rm th shift after 12 h of the clock stressing with lower frequency (167 Hz) is about 12% slower speed than that of the stressing clock with higher frequency (16.7 kHz) under the high temperature (60 ^{\circ}\hbox{C} ).
原文 | English |
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文章編號 | 7005398 |
頁(從 - 到) | 633-639 |
頁數 | 7 |
期刊 | IEEE/OSA Journal of Display Technology |
卷 | 11 |
發行號 | 8 |
DOIs | |
出版狀態 | Published - 1 8月 2015 |