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Design and realisation of a new hardware efficient IP core for the 1-D discrete Fourier transform
C. D. Chien
*
, C. C. Lin, C. H. Yang,
Jiun-In Guo
*
此作品的通信作者
電子研究所
研究成果
:
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同行評審
6
引文 斯高帕斯(Scopus)
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Keyphrases
Hardware Efficiency
100%
Intellectual Property Core
100%
Discrete Fourier Transform
100%
Modern Hardware
100%
Low Computational Complexity
14%
Algorithmic Level
14%
Architectural Level
14%
System Integrator
14%
On-chip Applications
7%
Design Approach
7%
MPEG
7%
Signal-to-noise
7%
Efficient Implementation
7%
Intellectual Property
7%
Multimedia Applications
7%
Audio
7%
Word-level
7%
Hardware Cost
7%
System-on-chip Design
7%
Cyclic Convolution
7%
Verilog
7%
Filter Method
7%
Bit Level
7%
Design for Environment
7%
Addition Operation
7%
Radix
7%
Graphic User Interface
7%
Complex Constants
7%
Core Design
7%
Parameter Configuration
7%
Shift Operation
7%
Computation Sharing
7%
Timing Performance
7%
Soft Core
7%
Discrete Fourier Transform Coefficients
7%
Automatic Generation
7%
Design Exploration
7%
Constant multiplication
7%
Parallel Output
7%
Code Synthesis
7%
Finite Wordlength Effect
7%
Artificial Reverberation
7%
Engineering
Realization
100%
One Dimensional
100%
Intellectual Property Core
100%
Dimensional Discrete
100%
Discrete Fourier Transform
100%
Fourier Transform Design
25%
Hardware Cost
18%
System-on-Chip
12%
Architectural Level
12%
System Integrator
12%
Addition Operation
6%
MPEG
6%
Efficient Implementation
6%
Cyclic Convolution
6%
Design Environment
6%
Artificial Reverberation
6%
User Interfaces
6%
Computer Science
Fourier Transform
100%
Dimensional Discrete
100%
Computer Hardware
100%
Hardware Cost
20%
Architectural Level
13%
System Integrator
13%
System-on-Chip
13%
MPEG
6%
Efficient Implementation
6%
Multimedia Application
6%
Density Functional Theory
6%
Cyclic Convolution
6%
Testbench
6%
Configuration Parameter
6%
Graphic User Interface
6%
Automatic Generation
6%
Design Exploration
6%