Design and optimization methodology for 3D RRAM arrays

Yexin Deng, Hong Yu Chen, Bin Gao, Shimeng Yu, Shih Chieh Wu, Liang Zhao, Bing Chen, Zizhen Jiang, Xiaoyan Liu, Tuo-Hung Hou, Yoshio Nishi, Jinfeng Kang, H. S.Philip Wong

    研究成果: Conference contribution同行評審

    28 引文 斯高帕斯(Scopus)

    摘要

    3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

    原文English
    主出版物標題2013 IEEE International Electron Devices Meeting, IEDM 2013
    頁面25.7.1-25.7.4
    頁數4
    DOIs
    出版狀態Published - 9 12月 2013
    事件2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
    持續時間: 9 12月 201311 12月 2013

    出版系列

    名字Technical Digest - International Electron Devices Meeting, IEDM
    ISSN(列印)0163-1918

    Conference

    Conference2013 IEEE International Electron Devices Meeting, IEDM 2013
    國家/地區United States
    城市Washington, DC
    期間9/12/1311/12/13

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