TY - GEN
T1 - Design and implementation of synchronization detection for IEEE 802.15.3c
AU - Huang, Ya Shiue
AU - Liu, Wei Chang
AU - Jou, Shyh-Jye
PY - 2011
Y1 - 2011
N2 - In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).
AB - In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).
UR - http://www.scopus.com/inward/record.url?scp=79959521001&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2011.5783583
DO - 10.1109/VDAT.2011.5783583
M3 - Conference contribution
AN - SCOPUS:79959521001
SN - 9781424484997
T3 - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
SP - 83
EP - 86
BT - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
T2 - 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Y2 - 25 April 2011 through 28 April 2011
ER -