Design and implementation of synchronization detection for IEEE 802.15.3c

Ya Shiue Huang*, Wei Chang Liu, Shyh-Jye Jou

*此作品的通信作者

    研究成果: Conference contribution同行評審

    9 引文 斯高帕斯(Scopus)

    摘要

    In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).

    原文English
    主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    頁面83-86
    頁數4
    DOIs
    出版狀態Published - 2011
    事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
    持續時間: 25 4月 201128 4月 2011

    出版系列

    名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

    Conference

    Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    國家/地區Taiwan
    城市Hsinchu
    期間25/04/1128/04/11

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