TY - GEN
T1 - Design and implementation of reconfigurable RSA cryptosystem
AU - Chen, Yun Lu
AU - Tseng, Chih Yeh
AU - Chang, Hsie-Chia
PY - 2007/9/28
Y1 - 2007/9/28
N2 - In this paper, the hardware implementation of a reconfigurable RSA cryptosystem is presented. In order to match distinct security levels, the modified Montgomery modular multiplication algorithm is introduced into this 512/1024/2048/4096-bits RSA encryption/decryption. The huge number of register is also replaced by 5 memory blocks. As a result, our design including 5 memory blocks achieves the baud rate of 99kb/s for 512-bit, 29kb/s for 1024-bit, 6.8ks/b for 2048-bit and 1.7kb/s for 4096-bit on Xilinx Vertex2 XC2V8000 of 6783 slices.
AB - In this paper, the hardware implementation of a reconfigurable RSA cryptosystem is presented. In order to match distinct security levels, the modified Montgomery modular multiplication algorithm is introduced into this 512/1024/2048/4096-bits RSA encryption/decryption. The huge number of register is also replaced by 5 memory blocks. As a result, our design including 5 memory blocks achieves the baud rate of 99kb/s for 512-bit, 29kb/s for 1024-bit, 6.8ks/b for 2048-bit and 1.7kb/s for 4096-bit on Xilinx Vertex2 XC2V8000 of 6783 slices.
UR - http://www.scopus.com/inward/record.url?scp=34648836565&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2007.373258
DO - 10.1109/VDAT.2007.373258
M3 - Conference contribution
AN - SCOPUS:34648836565
SN - 1424405831
SN - 9781424405831
T3 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
BT - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
T2 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Y2 - 25 April 2007 through 27 April 2007
ER -